Semiconductor device and method of manufacture thereof

ABSTRACT

A semiconductor device includes an insulating substrate, a wiring pattern formed on the insulating substrate, a semiconductor chip secured to the wiring pattern, a junction terminal formed of the same material as the wiring pattern and electrically connected to the semiconductor chip, one end of the junction terminal being secured to the insulating substrate, the other end of the junction terminal extending upward away from the insulating substrate, and a control circuit for transmitting a control signal for the semiconductor chip, the control circuit being electrically connected to the junction terminal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device used, e.g., forhigh power switching, etc., and a method of manufacture thereof.

2. Background Art

Japanese Laid-Open Patent Publication No. 2002-315357 discloses asemiconductor device in which metal plates serving as wiring patternsare formed on an insulating substrate. Connection terminals are securedto the wiring patterns and extend upward away from the insulatingsubstrate. The connection terminals are used to connect thesemiconductor device and external components.

The manufacturing process for the semiconductor device disclosed in theabove publication is complicated, since the connection terminals aresecured onto the wiring patterns. As a result, the semiconductor devicedisclosed in the publication is costly to produce.

SUMMARY OF THE INVENTION

The present invention has been made to solve the foregoing problem. Itis, therefore, an object of the present invention to provide asemiconductor device suitable for being manufactured at a reduced cost,and a method of manufacture thereof. The features and advantages of thepresent invention may be summarized as follows.

According to one aspect of the present invention, a semiconductor deviceincludes an insulating substrate, a wiring pattern formed on theinsulating substrate, a semiconductor chip secured to the wiringpattern, a junction terminal formed of the same material as the wiringpattern and electrically connected to the semiconductor chip, one end ofthe junction terminal being secured to the insulating substrate, theother end of the junction terminal extending upward away from theinsulating substrate, and a control circuit for transmitting a controlsignal for the semiconductor chip, the control circuit beingelectrically connected to the junction terminal.

According to another aspect of the present invention, a semiconductordevice includes an insulating substrate, a wiring pattern formed on theinsulating substrate and including a first wiring pattern, a secondwiring pattern, and a third wiring pattern, a semiconductor chip securedto the first wiring pattern, a junction terminal electrically connectedto the semiconductor chip, one end of the junction terminal beingembedded in the second wiring pattern, the other end of the junctionterminal extending upward away from the insulating substrate, a controlcircuit for transmitting a control signal for the semiconductor chip,the control circuit being electrically connected to the junctionterminal, and a power terminal electrically connected to thesemiconductor chip, one end of the power terminal being embedded in thethird wiring pattern, the other end of the power terminal extendingupward away from the insulating substrate.

According to another aspect of the present invention, a method ofmanufacturing a semiconductor device, includes a step of placing aninsulating substrate in a mold having a wiring pattern-forming cavityfor forming a wiring pattern on the insulating substrate and also havinga junction terminal-forming cavity for forming a junction terminalextending upward from the insulating substrate, an aluminum pouring stepof pouring aluminum into the wiring pattern-forming cavity and thejunction terminal-forming cavity, and a step of cooling the aluminum.

Other and further objects, features and advantages of the invention willappear more fully from the following description.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a semiconductor device in accordancewith a first embodiment of the present invention;

FIG. 2 is a diagram showing the molds, etc. used by the semiconductordevice manufacturing method of the first embodiment;

FIG. 3 is a cross-sectional view of the semiconductor device of thesecond embodiment;

FIG. 4 is a diagram showing the molds, etc. used by the semiconductordevice manufacturing method of the second embodiment;

FIG. 5 is a cross-sectional view of the semiconductor device of thethird embodiment;

FIG. 6 is a cross-sectional view of the semiconductor device of thefourth embodiment;

FIG. 7 is a cross-sectional view of the semiconductor device of thefifth embodiment;

FIG. 8 is a cross-sectional view of the semiconductor device of thesixth embodiment;

FIG. 9 is a diagram showing the molds, etc. used by the semiconductordevice manufacturing method of the sixth embodiment;

FIG. 10 is a cross-sectional view showing a semiconductor device inwhich a control circuit is secured onto a wiring pattern;

FIG. 11 is a cross-sectional view showing a semiconductor deviceprovided with a molded resin; and

FIG. 12 is a cross-sectional view showing a semiconductor deviceprovided with an adhesive primer.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment

FIG. 1 is a cross-sectional view of a semiconductor device in accordancewith a first embodiment of the present invention. The semiconductordevice 10 includes an insulating substrate 12. The insulating substrate12 is formed, e.g., of AlN, Al₂O₃, SiN, etc. Wiring patterns 14 a and 14b are formed on the insulating substrate 12. A junction terminal 14 c isalso formed on the insulating substrate 12. One end of the junctionterminal 14 c is secured to the insulating substrate 12, and the otherend of the junction terminal 14 c extends upward away from theinsulating substrate 12. The junction terminal 14 c is formed of thesame material as the wiring patterns 14 a and 14 b.

A bottom surface pattern 16 is formed on the bottom surface of theinsulating substrate 12. The bottom surface pattern 16 and the wiringpatterns 14 a and 14 b are formed of aluminum 1-5 mm thick. Asemiconductor chip 20 is secured to the wiring pattern 14 b by solder18. The semiconductor chip 20 is configured, e.g., from an IGBT and adiode formed of silicon. The semiconductor chip 20 is electricallyconnected to the junction terminal 14 c and the wiring pattern 14 a bywires 22.

A case 26 is secured to the insulating substrate 12 by adhesives 24 aand 24 b. The case 26 is formed so as to outwardly expose the bottompattern 16. A power terminal 28 is formed along an inner wall of thecase 26. The power terminal 28 is electrically connected to thesemiconductor chip 20 by wires 22.

Silicon gel 30 is disposed within the case 26. The silicon gel 30 sealsthe semiconductor chip 20. The junction terminal 14 c and the powerterminal 28 extend through and outwardly from the silicon gel 30.Outside the silicon gel 30, a control substrate 32 is connected to thejunction terminal 14 c. A control circuit 34 is secured to the controlsubstrate 32. The control circuit 34 is electrically connected to thejunction terminal 14 c and transmits a control signal for thesemiconductor chip 20. A cover 38 for the case 26 is mounted above thecontrol substrate 32. A control terminal 40 is secured to the controlsubstrate 32. The control terminal 40 extends through and outwardly fromthe cover 38.

A method of manufacturing a semiconductor device in accordance with thefirst embodiment will now be described. FIG. 2 is a diagram showing themolds, etc. used by the semiconductor device manufacturing method of thefirst embodiment. The wiring patterns 14 a and 14 b, the junctionterminal 14 c, the bottom pattern 16 described above are formed bycasting. Specifically, they are formed by use of molds 42 and 44. Themold 42 has formed therein wiring pattern-forming cavities 14 a′ and 14b′ for forming the wiring patterns 14 a and 14 b, respectively, on theinsulating substrate 12. The mold 42 also has formed therein a junctionterminal-forming cavity 14 c′ for forming the junction terminal 14 cwhich extends upward from the insulating substrate. The mold 44 hasformed therein a bottom surface pattern-forming cavity 16′ for formingthe bottom surface pattern 16. The following steps are performed usingthe molds 42 and 44.

First, the insulating substrate 12 is placed in a cavity formed by themolds 42 and 44. Molten aluminum is then poured into the wiringpattern-forming cavities 14 a′ and 14 b′, the junction terminal-formingcavity 14 c′, and the bottom surface pattern-forming cavity 16′. Thisstep is referred to as the aluminum pouring step. Next, the pouredaluminum is cooled. The molds 42 and 44 are then removed from thecasting, i.e., the insulating substrate 12 having the wiring patterns 14a and 14 b, the junction terminal 14 c, and the bottom pattern 16 formedthereon. The semiconductor chip 20 is then soldered to the wiringpattern 14 b, and then other steps are performed to form thesemiconductor device 10 shown in FIG. 1.

The semiconductor device of the first embodiment is configured such thatthe junction terminal 14 c can be formed at the same time as the wiringpatterns 14 a and 14 b, etc. by casting. Therefore, the semiconductordevice can be manufactured without the step of securing the junctionterminal to a wiring pattern, making it possible to manufacture thesemiconductor device at a reduced cost.

Second Embodiment

A semiconductor device and a method of manufacture thereof in accordancewith a second embodiment of the present invention have many featurescommon to the first embodiment. Therefore, the following description ofthe semiconductor device and the method of the second embodiment will beprimarily limited to the differences from the first embodiment. FIG. 3is a cross-sectional view of the semiconductor device of the secondembodiment. The semiconductor device 50 includes a power terminal 14 d.One end of the power terminal 14 d is secured to the insulatingsubstrate 12, and the other end extends upward away from the insulatingsubstrate 12. The power terminal 14 d is formed of the same material(aluminum) as the wiring pattern 14 b. That is, the power terminal 14 d,the wiring pattern 14 b, the junction terminal 14 c, and the bottompattern 16 are all formed of aluminum. It should be noted that the powerterminal 14 d is electrically connected to the semiconductor chip 20 bywires 22.

The method of manufacturing a semiconductor device in accordance withthe second embodiment will now be described. The semiconductor devicemanufacturing method of the second embodiment is basically similar tothat of the first embodiment, but uses a mold of a differentconfiguration. FIG. 4 is a diagram showing the molds, etc. used by thesemiconductor device manufacturing method of the second embodiment.Specifically, a mold 46 has formed therein a power terminal-formingcavity 14 d′ for forming the power terminal 14 d which extends upwardfrom the insulating substrate 12. In the aluminum pouring step, moltenaluminum is poured into the wiring pattern-forming cavity 14 b′, thejunction terminal-forming cavity 14 c′, the power terminal-formingcavity 14 d′, and the bottom surface pattern-forming cavity 16′. Itshould be noted that the power terminal 14 d which has been produced inthe power terminal-forming cavity 14 d′ is not yet in its final shape.After the mold 46 is removed from the casting, the portion of the powerterminal 14 d extending straight upward from the insulating substrate 12is bent into the desired shape, thereby completing the formation of thepower terminal 14 d. Thus, in the semiconductor device manufacturingmethod of the second embodiment, the wiring pattern 14 b, the junctionterminal 14 c, the power terminal 14 d, and the bottom surface pattern16 are formed by casting in the molds 44 and 46.

The semiconductor device and the method of manufacture thereof inaccordance with the second embodiment are configured such that thewiring pattern 14 b, the junction terminal 14 c, the power terminal 14d, and the bottom surface pattern 16 are cast at once. This simplifiesthe manufacturing process, making it possible to manufacture thesemiconductor device at a reduced cost.

Third Embodiment

A semiconductor device and a method of manufacture thereof in accordancewith a third embodiment of the present invention have many featurescommon to the first embodiment. Therefore, the following description ofthe semiconductor device and the method of the third embodiment will beprimarily limited to the differences from the first embodiment. FIG. 5is a cross-sectional view of the semiconductor device of the thirdembodiment. The semiconductor device 60 includes a control circuitwiring pattern 14 e formed on the insulating substrate 12. The controlcircuit wiring pattern 14 e is formed of the same material (aluminum) asthe wiring pattern 14 b. That is, the control circuit wiring pattern 14e, the power terminal 14 d, the wiring pattern 14 b, the junctionterminal 14 c, and the bottom surface pattern 16 are all formed ofaluminum. A control circuit 34 is secured to the control circuit wiringpattern 14 e. The control circuit 34 is connected to the semiconductorchip 20 and the junction terminal 14 c by wires 22. Further, the controlcircuit 34 is sealed by silicon gel 30.

In the semiconductor device of the third embodiment, the control circuit34 is secured to the control circuit wiring pattern 14 e, therebyeliminating the need for a control substrate. Further, in order to allowthe semiconductor chip to be connected to an external device, thesemiconductor device of the third embodiment includes the junctionterminal 14 c which performs the function of both the junction terminaland the power terminal of the semiconductor device shown in FIG. 1.Therefore, the semiconductor device of the third embodiment can bemanufactured at a reduced cost.

Fourth Embodiment

A semiconductor device and a method of manufacture thereof in accordancewith a fourth embodiment of the present invention have many featurescommon to the third embodiment. Therefore, the following description ofthe semiconductor device and the method of the fourth embodiment will beprimarily limited to the differences from the third embodiment. FIG. 6is a cross-sectional view of the semiconductor device of the fourthembodiment. The semiconductor device 70 is provided with a molded resin72. The molded resin 72 covers the insulating substrate 12, the wiringpattern 14 b, the control circuit wiring pattern 14 e, the semiconductorchip 20, the junction terminal 14 c, the control circuit 34, and thepower terminal 14 d, and outwardly exposes the surface of the bottomsurface pattern 16 opposite that in contact with the insulatingsubstrate 12, the distal end of the junction terminal 14 c, and thedistal end of the power terminal 14 d. The coefficient of linearexpansion of the molded resin 72 is equal to that of the wiring pattern14 b (i.e., the coefficient of linear expansion of aluminum).

The semiconductor device 70 of the fourth embodiment is provided withthe molded resin 72, which eliminates the need for a case, a cover, andsilicon gel, such as those provided in the semiconductor device of thethird embodiment, making it possible to manufacture the semiconductordevice at a. reduced cost. It should be noted that semiconductor devicesof the type described herein are configured such that the bottom surfacepattern on the bottom surface of the insulating substrate has a muchlarger surface area than the wiring patterns on the top surface of theinsulating substrate. This means that the amount of aluminum on thebottom surface of the insulating substrate is much greater than that onthe top surface of the insulating substrate. As a result it has beenfound in some cases that the insulating substrate warps convex upwarddue to the shrinkage of the bottom surface pattern caused by the coolingof the pattern after heating. In the case of the semiconductor device ofthe fourth embodiment, however, all the materials surrounding theinsulating substrate have equal coefficients of linear expansion, sincethe coefficient of linear expansion of the molded resin 72 is equal tothat of the wiring pattern 14 b, making it possible to prevent warpageof the insulating substrate 12.

Although the constituent materials of the molded resin 72 have not beenspecified, it is to be understood that the molded resin 72 may be epoxyresin containing a filler such as glass or silica. The use of such afiller makes it easy to adjust the coefficient of linear expansion ofthe molded resin 72 to be equal to that of aluminum. Alternatively, themolded resin 72 may be an optimum type of resin for that purpose anddoes not contain filler. For example, the molded resin 72 may be phenolresin. It should be noted that the only requirement for the coefficientof linear expansion of the molded resin 72 is that it be sufficientlyclose to the coefficient of linear expansion of aluminum to preventwarpage of the insulating substrate 12. Therefore, the coefficient oflinear expansion of the molded resin 72 need not be equal to that ofaluminum if it is possible to prevent warpage of the insulatingsubstrate 12.

Fifth Embodiment

A semiconductor device and a method of manufacture thereof in accordancewith a fifth embodiment of the present invention have many featurescommon to the fourth embodiment. Therefore, the following description ofthe semiconductor device and the method of the fifth embodiment will beprimarily limited to the differences from the fourth embodiment. FIG. 7is a cross-sectional view of the semiconductor device of the fifthembodiment. The semiconductor device 74 includes an adhesive primer 76formed on the surface of the wiring patterns (of aluminum) and on thesurface of the insulating substrate 12. The adhesive primer 76 serves toincrease the adhesion between the molded resin 72 and the insulatingsubstrate 12. Thus in the semiconductor device of the fifth embodiment,substantial adhesion between the molded resin 72 and the insulatingsubstrate 12 is ensured by use of the adhesive primer 76.

Sixth Embodiment

A semiconductor device and a method of manufacture thereof in accordancewith a sixth embodiment of the present invention have many featurescommon to the first embodiment. Therefore, the following description ofthe semiconductor device and the method of the sixth embodiment will beprimarily limited to the differences from the first embodiment. FIG. 8is a cross-sectional view of the semiconductor device of the sixthembodiment. The semiconductor device 80 is characterized in that one endof a junction terminal 82 and one end of a power terminal 84 areembedded in their respective wiring patterns.

The insulating substrate 12 has a first wiring pattern 14 f, a secondwiring pattern 14 g, and a third wiring pattern 14 h formed thereon. Thefirst wiring pattern 14 f, the second wiring pattern 14 g, and the thirdwiring pattern 14 h are sometimes hereinafter referred to collectivelyas the “wiring patterns.” The semiconductor chip 20 is secured onto thefirst wiring pattern 14 f.

The semiconductor device 80 is provided with the junction terminal 82.One end of the junction terminal 82 is embedded in the second wiringpattern 14 g, and the other end of the junction terminal 82 extendsupward away from the insulating substrate 12 and is connected to thecontrol substrate 32. The junction terminal 82 is electrically connectedto the semiconductor chip 20 by way of the second wiring pattern 14 gand a wire 22. The control circuit 34, which transmits a control signalfor the semiconductor chip 20, is electrically connected to the otherend (i.e., the distal end) of the junction terminal 82.

The semiconductor device 80 is also provided with the power terminal 84.One end of the power terminal 84 is embedded in the third wiring pattern14 h, and the other end of the power terminal 84 extends upward awayfrom the insulating substrate 12. The power terminal 84 is electricallyconnected to the semiconductor chip 20.

FIG. 9 is a diagram showing the molds, etc. used by the semiconductordevice manufacturing method of the sixth embodiment. Specifically, themethod uses the mold 44 (described above in connection with the firstembodiment) and a mold 86. The mold 86 has formed therein a first wiringpattern-forming cavity 14 f′ for forming the first wiring pattern 14 f,a second wiring pattern-forming cavity 14 g′ for forming the secondwiring pattern 14 g, and a third wiring pattern-forming cavity 14 h′ forforming the third wiring pattern 14 h. The first wiring pattern 14 f,the second wiring pattern 14 g, the third wiring pattern 14 h, and thebottom surface pattern 16 are formed on the insulating substrate 12using the molds 44 and 86. More specifically, molten aluminum is pouredinto the molds 44 and 86 with the junction terminal 82 and the powerterminal 84 inserted into the mold 86 so that one end of the junctionterminal 82 is embedded into the second wiring pattern 14 g and one endof the power terminal 84 is embedded into the third wiring pattern 14 h.It should be noted that when the mold 86 has been removed from thecasting, the power terminal 14 d is not yet in its final shape andextends straight upward from the insulating substrate 12. Therefore,after the removal of the mold 86, the power terminal 14 d is bent intoits final shape.

The semiconductor device and the method of manufacture thereof inaccordance with the sixth embodiment are configured such that thejunction terminal 82 and the power terminal 84 are secured to wiringpatterns at the same time as when the wiring patterns are formed, makingit possible to simplify the manufacturing process. It should be notedthat it has been found difficult to form, at a reasonable cost, a moldfor forming a junction terminal and a power terminal if these terminalshave a complicated shape. In the semiconductor device and the method ofmanufacture thereof in accordance with the sixth embodiment, however,the junction terminal and the power terminal are embedded in wiringpatterns, thereby eliminating the need to match the shape of the moldsto that of the junction terminal and the power terminal. This makes itpossible to manufacture semiconductor devices having a junction terminaland a power terminal of a complicated configuration by a simple process.

The semiconductor device and the method of manufacture thereof inaccordance with the sixth embodiment may be combined with theabove-described various techniques to further reduce cost. FIG. 10 is across-sectional view showing a semiconductor device in which a controlcircuit is secured onto a wiring pattern. This configuration does notrequire a control substrate, resulting in a reduced cost. FIG. 11 is across-sectional view showing a semiconductor device provided with amolded resin. The use of the molded resin 72 eliminates the need for acase, a cover, and silicon gel, such as those provided in thesemiconductor device of the first embodiment, resulting in a reducedcost. FIG. 12 is a cross-sectional view showing a semiconductor deviceprovided with an adhesive primer. This configuration results in improvedreliability, as compared to the configuration shown in FIG. 11.

Although in the first to sixth embodiments described above thesemiconductor chip 20 is formed of silicon, it is to be understood thatit may be formed of a wide bandgap semiconductor having a wider bandgapthan silicon. Examples of wide bandgap semiconductors include siliconcarbide, gallium nitride-based materials, and diamond. IGBTs and diodesformed of wide bandgap semiconductor have a high maximum allowablecurrent density, making it possible to reduce their size.

In accordance with the present invention, there are providedsemiconductor devices suitable for being manufactured at a reduced cost,and a method of manufacture thereof.

Obviously many modifications and variations of the present invention arepossible in the light of the above teachings. It is therefore to beunderstood that within the scope of the appended claims the inventionmay be practiced otherwise than as specifically described.

The entire disclosure of a Japanese Patent Application No. 2011-214412,filed on Sep. 29, 2011 including specification, claims, drawings andsummary, on which the Convention priority of the present application isbased, are incorporated herein by reference in its entirety.

What is claimed is:
 1. A semiconductor device comprising: an insulatingsubstrate; a wiring pattern formed on said insulating substrate; asemiconductor chip secured to said wiring pattern; a junction terminalformed of the same material as said wiring pattern and electricallyconnected to said semiconductor chip, one end of said junction terminalbeing secured to said insulating substrate, the other end of saidjunction terminal extending upward away from said insulating substrate;and a control circuit for transmitting a control signal for saidsemiconductor chip, said control circuit being electrically connected tosaid junction terminal.
 2. The semiconductor device according to claim1, further comprising: a power terminal formed of the same material assaid wiring pattern and electrically connected to said semiconductorchip, one end of said power terminal being secured to said insulatingsubstrate, the other end of said power terminal extending upward awayfrom said insulating substrate.
 3. A semiconductor device comprising: aninsulating substrate; a wiring pattern formed on said insulatingsubstrate and including a first wiring pattern, a second wiring pattern,and a third wiring pattern; a semiconductor chip secured to said firstwiring pattern; a junction terminal electrically connected to saidsemiconductor chip, one end of said junction terminal being embedded insaid second wiring pattern, the other end of said junction terminalextending upward away from said insulating substrate; a control circuitfor transmitting a control signal for said semiconductor chip, saidcontrol circuit being electrically connected to said junction terminal;and a power terminal electrically connected to said semiconductor chip,one end of said power terminal being embedded in said third wiringpattern, the other end of said power terminal extending upward away fromsaid insulating substrate.
 4. The semiconductor device according toclaim 1, further comprising a control circuit wiring pattern formed ofthe same material as said wiring pattern and provided on said insulatingsubstrate, wherein said control circuit is secured to said controlcircuit wiring pattern.
 5. The semiconductor device according to claim2, further comprising: a bottom surface pattern formed on a bottomsurface of said insulating substrate; and a molded resin covering saidinsulating substrate, said wiring pattern, said semiconductor chip, saidjunction terminal, said control circuit, and said power terminal, andoutwardly exposing said other end of said junction terminal, said otherend of said power terminal, and the surface of said bottom surfacepattern opposite that in contact with said insulating substrate.
 6. Thesemiconductor device according to claim 2, further comprising: a bottomsurface pattern formed on a bottom surface of said insulating substrate;an adhesive primer formed on a surface of said wiring pattern and asurface of said insulating substrate; and a molded resin covering saidinsulating substrate, said wiring pattern, said primer, saidsemiconductor chip, said junction terminal, said control circuit, andsaid power terminal, and outwardly exposing said other end of saidjunction terminal, said other end of said power terminal, and thesurface of said bottom surface pattern opposite that in contact withsaid insulating substrate.
 7. The semiconductor device according toclaim 5, wherein the coefficient of linear expansion of said moldedresin is equal to that of said wiring pattern.
 8. The semiconductordevice according to claim 1, wherein said semiconductor chip is formedof a wide bandgap semiconductor.
 9. The semiconductor device accordingto claim 8, wherein said wide bandgap semiconductor is silicon carbide,gallium nitride-based material, or diamond.
 10. A method ofmanufacturing a semiconductor device, comprising: a step of placing aninsulating substrate in a mold having a wiring pattern-forming cavityfor forming a wiring pattern on said insulating substrate and alsohaving a junction terminal-forming cavity for forming a junctionterminal extending upward from said insulating substrate; an aluminumpouring step of pouring aluminum into said wiring pattern-forming cavityand said junction terminal-forming cavity; and a step of cooling saidaluminum.
 11. The method according to claim 10, wherein: said mold has apower terminal-forming cavity for forming a power terminal extendingupward from said insulating substrate; and said aluminum pouring stepincludes pouring aluminum into said power terminal-forming cavity.